Typical Problems In Foundry Model Sets

Below is a list from a single set of foundry-provided models. 

Problems in Resistors:

  • Thermal coefficients not present
  • Perimeter capacitance not there
  • Bottom to bulk capacitance not there
  • Variance as a bias function not done for n-well resistors
  • Geometry scaling not valid
  • Corner models not properly set

Problem in Diodes:

  • Dielectric leakage not represented
  • No transit time in model
  • No flicker noise in model
  • Body resistance not included
  • No Body/Substrate capacitance
  • Unlimited geometry scaling, that is only valid at a single point

Problems in Capacitors:

  • Dielectric leakage not represented
  • No Bottom plate capacitor
  • No Top/Fringe capacitor

Problems with planar spiral inductors:

  • Parasitic capacitance not properly specified
  • Eddy current losses not considered
  • No Electromagnetic modeling or empirical analysis for validation
  • No capacitance to represent the cross under metal path
  • Requirements for guard bands that are not needed

Problems with CMOS transistors:

  • Capacitor elements not distributed as per the physical model
  • N-Well underneath PMOS not represented or defined
  • Resistance of gate stripe not included
  • Parameters left out of the model, and the ideal case is assumed by the simulator
  • Parameters set to zero, which does not correspond to the physical model
  • Sub threshold currents never measured and fit into the model
  • Breakdown and overvoltage parameters not in the model

What Other Model Problems Are There?

In addition to problems with semiconductor primitive models, common design problems are interference noise coupling and implicit items left out of simulations. See the white papers on these subjects.

Effective Electrons performs foundry model audits to help teams understand the problems and define model patches for quick results. As well, our training programs teach the necessary techniques.

For more information contact us.


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